8xx v2.6 TLB problems and suggested workaround

[Pantelis Antoniou]

Dan Malek wrote:
> 
> On Apr 4, 2005, at 3:17 PM, Marcelo Tosatti wrote:
> 
>> Problem is that the "dcbst" instruction will, _sometimes_ (the 
>> failure/success rate is about 1/4
>> with my test application) fault as a _write_ operation on the data.
> 
> 
> Oh, geeze .... It's all coming back to me now ....
> 
> The 8xx cache operations don't always operate as defined in the PEM.
> There are likely to be some archive discussions within the Freescale
> knowledge data base that describe the different behaviors I've seen
> with the chip variants and revisions.  I can't find any of those e-mail
> discussions, so I'll try to recall from memory.
> 
> The PEM cache instructions are all implemented in a microcode that
> uses the 8xx unique cache control SPRs.  Depending upon the state
> of the cache and MMU, it seems in some cases the EA translation is
> subject to a "normal" protection match instead of a load operation match.
> 

OK, maybe we should make 8xx specifics cache flushing functions, that
use the SPR, and forget about this mess.

However is this problem also triggered by user space? If it is we should
try to maintain compatibility...

> The behavior of these operations isn't consistent across all of the 8xx
> processor revisions, especially with early silicon if people are still
> using those.  During conversations with Freescale engineers, it seems
> the only guaranteed operation was to use the 8xx unique SPRs, but
> I think I only did that in 8xx specific functions.
> 
> We have way too much code in the TLB exception handlers already,
> so let's just try a tlbia of the EA in the update_mmu_cache, with an #ifdef
> for the 8xx.  It seems if the dcbst causes a TLB miss during execution,
> it does the right thing.  We may want to make the dcbxxx instructions some
> kind of macro, so on 8xx we can include such operations in otherwise
> "standard" software.
> 
> Thanks for the great work!
> 
> 
>     -- Dan
> 
> 
> 

Regards

Pantelis