8xx v2.6 TLB problems and suggested workaround

[Marcelo Tosatti]

Hum,

The machine seems to be acting strange, but it boots normally 
and applications run (more importantly there is no TLB entry 
which could cause dcbst fault strangeness).

Some "dd" hangs till I press "ctrl+c", others just work. Really strange. 

G'night, I'll look at it tomorrow.
 
[root@(none) /]# time dd if=/dev/zero of=file bs=16k count=400
400+0 records in
400+0 records out
                                                                                        
real    0m4.261s
user    0m0.040s
sys     0m1.240s
[root@(none) /]# time dd if=/dev/zero of=file bs=32k count=400
                                                                                        
                                                                                        
real    0m50.369s
user    0m0.040s
sys     0m1.680s  (ctrl+c)
[root@(none) /]# 


> --- a/arch/ppc/kernel/head_8xx.S.orig	2005-04-04 19:43:23.000000000 -0300
> +++ b/arch/ppc/kernel/head_8xx.S	2005-04-04 19:47:40.000000000 -0300
> @@ -359,9 +359,7 @@
>  
>  	. = 0x1200
>  DataStoreTLBMiss:
> -#ifdef CONFIG_8xx_CPU6
>  	stw	r3, 8(r0)
> -#endif
>  	DO_8xx_CPU6(0x3f80, r3)
>  	mtspr	M_TW, r10	/* Save a couple of working registers */
>  	mfcr	r10
> @@ -390,6 +388,16 @@
>  	mfspr	r10, MD_TWC	/* ....and get the pte address */
>  	lwz	r10, 0(r10)	/* Get the pte */
>  
> +	li	r3, 0
> +	cmpw	r10, r3            /* does the pte contain a valid address? */
> +	bne	4f
> +	mfspr   r10, M_TW       /* Restore registers */
> +	lwz     r11, 0(r0)
> +	mtcr    r11
> +	lwz     r11, 4(r0)
> +	lwz	r3, 8(r0)
> +	b DataAccess
> +4:
>  	/* Insert the Guarded flag into the TWC from the Linux PTE.
>  	 * It is bit 27 of both the Linux PTE and the TWC (at least
>  	 * I got that right :-).  It will be better when we can put
> @@ -419,9 +427,7 @@
>  	lwz	r11, 0(r0)
>  	mtcr	r11
>  	lwz	r11, 4(r0)
> -#ifdef CONFIG_8xx_CPU6
>  	lwz	r3, 8(r0)
> -#endif
>  	rfi
>  
>  /* This is an instruction TLB error on the MPC8xx.  This could be due