PPC405GP: Spurious interrupt during handing level triggered interrupts

[listmember at orkun.us]

Kenneth,

Thanks for replying. I was happy to find your earlier thread during my
list archive search. I though about using something like your sequence
below but finally settled in ack_irq().

> /* We have to do this manually as enable do not do this for us */
> void mask_SR(int dev_irq){
>
> 	int bit;
> 	bit = (dev_irq-17) +25;
>
> 	mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit)));
> }
> --
> basically parts of what irq_ack would do (dev_irq is a privat number
> local to this driver)
>
> Perhaps the enable code should reset this bit also?? everyone that dose
> this type of userspace driver is going to hit this problem.

I think for edge triggered interrupts this would not be desirable if a
driver has sections that it cannot handle interrupts safely and disables
interrupts during such processing. If an interrupt arrived when interrupts
were disabled and enable actually reset the bit the interrupt would be
lost.

However, I think, code could be enhanced to reset the SR bit, "only" for
level triggered interrupts and leave edge triggered interrupts alone. This
would require looking at UIC0_TR register as well.

Best regards,
Tolunay

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