PCI Interrupt handling in Non-Monarch Mode

Karoliya, Abhishek Abhishek.Karoliya at fci.com
Tue Mar 2 02:26:03 EST 2004

Hi ,

     I am running Linux {Monta Vista's PE3.0 based on 2.4.18 and
Kernel.org's 2.4.20} on a MPC7447+GT MV64360 in a PMC form factor. I have to
customise the LSP so that even this board does not enumerate  devices on the
PCI bus {That is done by another board } , it should be able to handle
interrupts generated by these devices when delivered.
    I proposed the following design to handle this...
a) block the call to pciauto_bus_scan() to prevent the board from
b) let the kernel call the pci_init() to build up the kernel data structure
for the pci by reading the headers of the devices enumerated by the other
      However block{modify???} call to all bios fixup routines which may
re-enumerate the values.

However I am not sure of the implication that can be there when ...
a) I presumed that the PCI region in the memory map {memory /IO} of the
enumerator board is subset of that of the Non-Monarch mode that is handling
the interrupts. Is this THE necessary condition?? Can there be a workaround
a mapping of some sort to take care of the difference ?? if yes where should
it be placed ??

b) I also presumed that once the normal data structures {pci_dev etc} and
bus tree is build properly , all the pci drivers will work in perfect
harmony with no tweaking required for them.

c)In a scenario where there are multiple Non-monarchs who all have
successfully build up the data structure for that PCI bus topography, any
one of them will be able to handle any interrupt from the attached device
when delivered to them.

d)Is there any side effects/extra conditions to be taken care of when used
on Dual processor boards with SMP enabled.

This is getting more complex than I can handle...
Calling for all PCI Guru's {Matt where are you } to help..

Thanks a million for your time

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