TLB and CSSBAR problems with MPC8540 and BDI2000

[Fahd Abidi]

Hi,

I have a customer trying to get kernel debugging working with the BDI2000,
currently he is experiencing this problem:

My board is crashing on this particular piece of code:

/* invalidate MMU L1/L2 */
/* Note: before invalidate MMU L1/L2, we read TLB1 Entry 0 and then
 * write it back immediately to fixup a bug(Errata CPU4)  for this
	initial
 * TLB1 entry 0,otherwise the TLB1 entry 0 will be invalidated.
 */
#if defined(CONFIG_MPC85xx_REV1)
	lis	r2,0x1000
	mtspr	MAS0,r2
	tlbre
	tlbwe
	isync
	li      r2, 0x001e
	mtspr   MMUCSR0, r2
	isync
#endif

I think my problem is all centered around TLB's and the CCSRBAR. I don't
know if the above code is part of the problem but at reset the cpu has
the CCSRBAR at 0xff700000 and there is a TLB entry mapped to its
location. My init code is moving the CCSRBAR and mapping a TLB to its
new location. I tried just moving the CCSRBAR back to its default
location. Do I also need to remap a TLB address to default location?

Thanks,
Matthew

Does anyone know the answer to this problem?

thanks,

Fahd


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