Interrupts on PPC 405Gr

MERRITT Nigel Nigel.Merritt at
Fri Feb 6 13:47:28 EST 2004

I am using an IBM PowerPC 405Gr and have been trying to set up IRQ5 as an interrupt.  My problem is that the UIC0_ER (interrupt enable) register is not being set by the request_irq call.  I have used enable_irq after request_irq but this also has no affect.  As this is from a driver, I have even tried setting the correct bit (bit 30 for IRQ 5) directly, by reading UIC0_ER, ORing bit 30 and writing the value back - reading and writing were performed using mfdcr and mtdcr.
I also use mtmsr to set the general interrupt enable bit (EE - bit 16)) in the MSR register.

Does anyone know of other calls that need to be made in order to allow the interrupt enable register to stay set?

   Nigel Merritt

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