Any restrictions on DMA address boundry?

[Bret Indrelee]

Just wanted to thank both Matt Porter and Roland Dreier for taking
the time to explain the situation.

I've aligned our buffers to 32 bytes on PPC and am in the process of
confirming the x86 snoop/coherency situation. Aligning it this way
makes the transfer slightly faster anyways, since the 8245 PCI
bridge will cause a disconnect at every 32-byte boundary on a
PCI burst read.

Since the work I'm doing is embedded and we use the same buffer
format between application and driver/kernel space, I'm using
a fixed number rather than L1_CACHE_BYTES. The define for L1_CACHE_BYTES
is only available (as it probably should be) only if you've defined
KERNEL.

-Bret

--
Bret Indrelee                 QLogic Corporation
Bret.Indrelee at qlogic.com      6321 Bury Drive, St 13, Eden Prairie, MN 55346


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