[Fwd: ppc4xx Ports]

[Jon Masters]

Jon Masters wrote:

| I think I mentioned before that I already fixed that for the port I am
| working on by incrementing next TLB entry by 2 if on Virtex II Pro.
| Actually if you check a post I made to comp.arch.fpga over the summer...
| I call it CONFIG_BROKEN_XILINX_TLB or something like that (other ports
| are now starting to fix that too) - several other errata too.

I also force TLB pinning on my port and modify where the kernel TLB
entries go while also forcing in a pinning for serial early on.

Montavista or someone added a patch to do that anyway now but remember I
am using stock kernels and none of the Montavista trees :-).

Cheers,

Jon.


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