ppc440 and i2c

Wolfgang Denk wd at denx.de
Tue Nov 18 19:22:43 EST 2003

In message <20031118080843.GA28129 at gate.ebshome.net> you wrote:
> Your problem sounds strange.

No. It's just that this version (out of 3 different in a total  of  5
messages  to  several  mailing lists I've seen so far!) does not even
explain the problem correctly.

It's just a known issue on the I2C bus.

> Are you saying that after 440GP _reset_ IIC line state affects 440 ?


> If bootstrap IIC is accidentaly activated you may get problems if you
> have non-compliant/not-properly-reset device on IIC0 bus.

The problem is an I2C Edge Condition which means that I2C devices may
be left in a write state if a read  was  occuring  and  the  CPU  was
reset. This may for example result in EEPROM data corruption.

Best regards,

Wolfgang Denk

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
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