DMA & cache coherency on 8245

[Callebaut Benoit]

I,
I have written DMA functions to do software initiateds  DMA transfers on the
8245. But I have some problem with cache I think.
I allocated the buffers for DMA, configure the DMA (I use no snooping) and
launch it.
There is only part of the data that are transfered when doing mem-mem dmas or
nothing at all when doing mem-pci transfers.
I tried to use invalidate_dcache_range on the block (allocated with
__get_free_pages ) but it crashed (Exception 0X300 (memory access)).
How can I be sure of the coherency of the cache ?

Thanks,
Benoit Callebaut

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