bootstrap of virtex-ii pro eval board ML300

Scott Anderson sanders at
Tue Jun 3 06:36:22 EST 2003

On Saturday, May 31, 2003, at 06:14  PM, 丁厚永 wrote:
\We have subscribe the ML300 demo board from xilinx,but it needs several
> months to arrive. I remember someone has done some work in virtex II
> pro demo boards.Will someone tell me some details about the bootstrap's
> procedure of such systems.

A quick high level description from my understanding:
There is a piece of Xilinx hardware called System ACE which reads
a rotary switch to determine which of eight possible files it
should load from the first partition (which must be a FAT partition)
of the IBM MicroDrive.  System ACE initializes the FPGA, processor
and memory by using the contents of this file to manipulate the
JTAG chain.  Xilinx provides tools so that you can combine an
ELF image (e.g. a Linux kernel) with an FPGA bitstream so that
when the processor comes out of reset, your image is already
loaded into memory ready to go.  For your development, I would
suggest using a JTAG debugger (specifically, the Abatron BDI2000)
to load your kernel into memory so that you don't have to keep
mucking with the MicroDrive.  Having the BDI2000 also gives you
a good tool for debugging the kernel and drivers.


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