405 TLB miss reduction

[Wolfgang Grandegger]

Hello,

we are suffering from TLB misses on a 405GP processor, eating up to
10% of the CPU power when running our (rather big) application. We
can regain a few percent by using the kernel option CONFIG_PIN_TLB
but we are thinking about further kernel modifications to reduce
TLB misses. What comes into my mind is:

 - using a kernel PAGE_SIZE of 8KB (instead of 4KB).
 - using large-page TLB entries.

Has anybody already investigated the effort or benefit of such
changes or knows about other (simple) measures (apart from
replacing the hardware)?

TIA.

Wolfgang.


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