External TA assertion timing on GPCM

Steven Scholz steven.scholz at imc-berlin.de
Mon Mar 25 18:54:54 EST 2002


I quotr from MPC860 User Man. Chapter 11.6 Bus Monitor
"...The timing mechanism is clocked by the system clock devided by
eight. The maximum value is 2040 system clocks..."

The bus monitor timing is set in Bits 16-23 of SYPCR.

Hope this helps,


>I would like to know if there is a maximum limit from the time CS is asserted (during a read/write operation) till TA is asserted by the device externally.

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