MDIO clock speed computation

[Jean-Denis Boyer]

Dan,

> I never expected to see someone run something like 46.5 MHz.

I agree, this might be impossible to achieve, since the PLL gain is an
integer. But the externcal clock does not necessarily have a frequency which
is a multiple of 1MHz.

For example, some of our 860T based boards have an external clock of
4096kHz, which is multiplied by 12, and yields a core clock of 49152MHz.

I don't know much about clock devices, but I guess there are many
possibilities.

> Will this work for all cases? :
>
> ((((bd->bi_intfreq + 4999999) / 2500000) / 2 ) & 0x3F ) << 1;

I hope so ;-)


--------------------------------------------
 Jean-Denis Boyer, B.Eng., System Architect
 Mediatrix Telecom Inc.
 4229 Garlock Street
 Sherbrooke (Québec)
 J1L 2C8  CANADA
 (819)829-8749 x241
--------------------------------------------

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