MDIO clock speed computation

[Jean-Denis Boyer]

Dan,

> try this (since the problem is the divisor register truncation):
>
> (((((bd->bi_intfreq + 500000) / 2500000) + 1) / 2 ) & 0x3F ) << 1;

This is bad :-(
With a frequency of 46.5MHz, you get a MII clock of 2.58MHz.

Why adding 500000 (0.5MHz) to the internal clock in this computation?
We usually do that to round up (or down) to the nearest integer.
But we do NOT want to round down, or the divisor (MII_SPEED) will be too
low.
We want to round up to the nearest integer when divided by 2*2.5MHz.

--------------------------------------------
 Jean-Denis Boyer, B.Eng., System Architect
 Mediatrix Telecom Inc.
 4229 Garlock Street
 Sherbrooke (Québec)
 J1L 2C8  CANADA
 (819)829-8749 x241
--------------------------------------------

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