PPC405gp enet Soft Reset

[andrew may]

On Mon, Feb 11, 2002 at 12:55:05PM +0100, David Müller (ELSOFT AG) wrote:
> Hi
>
> andrew may wrote:
> > Here is a log from ppcboot since it is easy to test this there without doing
> > a kernel build. My phy is at address 0x1f.
> >
> > => mii read 0x1 2
> > 07FF
> > => mii read 0x1 3
> > read err 3
> > a2: read: EMAC_STACR=0xffffc023, i=2
> > Error reading from the PHY
> > 07FF
> >
>
> I'm seeing this error too on our boards. But i'm not certain, if it's a
> problem of the MII controller in the 405 or a problem of the LXT971.
> What revision of the 405 do you have? What clock frequency your 405 run at?

Well since I have no phy at address 1 I expect to get an error, but the problem
is that I am not getting an error when the register number is even.

The phy is at address 0x1f since it was easier for our hw guy to tie all the pins
to the same thing rather than put it at low address.

It is a RevE chip running at 266Mhz, the phy is an AMD Am79C874/ Altima AC101.

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/