405LP EBC setup fix

[Hollis Blanchard]

EBC0_B0CR should be set as 16-bit; through an ifdef merging typo it is
currently set incorrectly as 8-bit. This prevents 405LP wakeup from
succeeding and needs to be fixed.

Please apply to _2_4_devel and 2.5.

-Hollis
-- 
PowerPC Linux
IBM Linux Technology Center
-------------- next part --------------
===== arch/ppc/platforms/beech.c 1.9 vs edited =====
--- 1.9/arch/ppc/platforms/beech.c	Thu Dec 12 17:06:37 2002
+++ edited/arch/ppc/platforms/beech.c	Tue Dec 17 11:29:58 2002
@@ -180,7 +180,7 @@
 	    (mfdcri(DCRN_EBC0, BnCR(0)) & EBC0_BnCR_MASK);
 	cr.fields.bs = BEECH_BANK0_EBC_SIZE;
 	cr.fields.bu = EBC0_BnCR_BU_RW;
-	cr.fields.bw = EBC0_BnCR_BW_8;
+	cr.fields.bw = EBC0_BnCR_BW_16;
 	mtdcri(DCRN_EBC0, BnCR(0), cr.reg);
 
 	ap.reg = mfdcri(DCRN_EBC0, BnAP(0)) & EBC0_BnAP_MASK;
-------------- next part --------------
===== arch/ppc/platforms/4xx/beech.c 1.9 vs edited =====
--- 1.9/arch/ppc/platforms/4xx/beech.c	Thu Dec 12 17:06:37 2002
+++ edited/arch/ppc/platforms/4xx/beech.c	Tue Dec 17 11:29:58 2002
@@ -180,7 +180,7 @@
 	    (mfdcri(DCRN_EBC0, BnCR(0)) & EBC0_BnCR_MASK);
 	cr.fields.bs = BEECH_BANK0_EBC_SIZE;
 	cr.fields.bu = EBC0_BnCR_BU_RW;
-	cr.fields.bw = EBC0_BnCR_BW_8;
+	cr.fields.bw = EBC0_BnCR_BW_16;
 	mtdcri(DCRN_EBC0, BnCR(0), cr.reg);
 
 	ap.reg = mfdcri(DCRN_EBC0, BnAP(0)) & EBC0_BnAP_MASK;