Another fix for xmon on non-standard MMU machines

[David Gibson]

On Mon, Sep 10, 2001 at 08:16:32PM -0400, Dan Malek wrote:
>
> David Gibson wrote:
>
> > ..... Turns out the TLB miss handler
> > was broken in that:
> >     a) it set the TLB writable bit based only the _PAGE_DIRTY bit, but
> > a page can be dirty but still write-protected - in particular this
> > happens during the COW of the stack, so the two processes were sharing
> > their stack.
>
> What the heck are you looking at????
>
> It sets _PAGE_DIRTY | _PAGE_ACCESSED based upon the setting of
> the _PAGE_RW.

No, the Data Store handler sets these - the TLB miss handler sets
nothing, so a read will never touch _PAGE_ACCESSED.  At least that's
the case in the linuxppc_2_4_devel tree I'm looking at, pulled some
time yesterday.

> If you get a Data Store exception (which would be the case trying
> to access a page that is write protected), and the page is not
> marked _PAGE_RW, it will call the heavyweight fault handler to
> fix this.....which is exactly what happens for copy-on-write.
> The _PAGE_DIRTY is an alias to the hardware write protect.  Setting
> this bit will allow a write operation.

*If* we get a Data Store exception.  If the page is dirty, but write
protected (which happens during a COW), the TLB miss handler will load
the dirty bit into the hardware write enable bit and we will never get
the Data Store exception.

> The purpose of the TLB miss handlers are to simply store the Linux
> PTE (or close approximation) into the hardware TLB.  It is up to
> the Linux MM to construct this properly, which it appears isn't happening.

Yes, but the TLB WR bit must be the logical and of the PTE dirty and
RW bits.

> These exception handlers worked perfectly in the 2.4.2 timeframe.
> Modifications to other areas of the kernel have caused problems, and
> we need to find them there, not hack around down at this level where
> we want minimal code.

Changes might have caused problems, but according to paulus having
pages with _PAGE_DIRTY set, but _PAGE_RW cleared is correct behaviour,
so the TLB miss handler must deal with it - it's not like it's a lot
of code.

--
David Gibson			| For every complex problem there is a
david at gibson.dropbear.id.au	| solution which is simple, neat and
				| wrong.  -- H.L. Mencken
http://www.ozlabs.org/people/dgibson


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