Odd behaviour with 860P and LXT970

[Dan Malek]

"Gessner, Matt" wrote:

> ..... It's the switching
> rates that causes the problem.

Take an o'scope and look at the clocks from the PHY to the FEC.  The
PHY is responsible for providing the data clocks, and there is nothing
from "our" side that is clock speed related (except the MDIO clock, which
isn't the concern here).  The only thing we have to know in the driver is
full/half duplex and reconfigure the FEC if necessary.

It almost sounds like the PHY didn't negotiate or determine the clock speed
correctly.  I tend to take the simple approach and always let the PHY
autonegotiate.  That is, I don't tell it with commands to use a particular
link speed, just read what it found.  The PHY command interface in the FEC
driver seems to be growing more complex and forcing modes of operation, when
I never did that in the original driver.

That's about all I can think of at this hour.


	-- Dan

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