Organisation of 4xx initialization code

[Mark Pilon]

Ralph Blach wrote:
>
> Just a note that might influence you.  The sprs of each 405 will be the same,
> but there is NO gurantee that the DCR, any of them look anything like any
> other DCR in any other DCR.
>
> I suggest core, chip, and then platform specfic.
>
> Chip
>

some differences between 405gp and 405pm:
- DCRs and memory mapped peripherals have moved, (m4xx_map_io(): makes
  more sense to map small blocks for each peripheral than one large
  map for 0x80000000 on up),

- the -PM supports floating point (yet more ifdefs for head_4xx.S)
- the ethernet MAL interrupts have been mux'd from 5 to 1 in the UIC
  (and moved too in the UIC -- more ifdefs for drivers/net/ppc4xx_enet.c)

IBM appears to create their processors by combining asic cores, i.e.
one core for the basic 405, one for ethernet, FPU, ... in doing so
they can move things around.  depending upon how many 4xx processors
they create, that's going to make for a lot of ifdefs if we stick to
one set of files.

is there a 'ppc-generic' set of interfaces that all code must conform
to in the kernel? too many layers?

an alternative might be (e.g.) all the ppc4xx ethernet stuff in
one file, but ifdef'd in (large separate) sections w/ common code
calling that which is processor specific.  (as opposed to ifdeffing
each individual func for each case.)

yow.

Mark
--
Mark Pilon

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