405GP and external masters

Brian Kuschak brian.kuschak at skystream.com
Tue Jul 10 07:26:31 EST 2001

I hope someone here has experience with the 405GP and external masters.
Regarding burst-capable External Bus Masters on the EBC on the 405GP ...

"Once an external master owns the peripheral interface it can read and write
all PLB- and OPB- addressable memory,
with the exception of devices controlled by the EBC."

If an external master initiates a burst write to an address in SDRAM, does
the the data go directly to SDRAM, or does it go to the cache instead?  I
would guess SDRAM since the 405 doesn't snoop.  Are there any other
restrictions on this type of transfer, other than the address being aligned
on a cache-line/burst boundary?  During the burst, is the PLB tied up for
longer than usual, since the burst is coming from a 50MHz bus onto a 200MHz
(PLB) bus, or does the EBC buffer this burst like the DMA controller does?

Thanks in advance.

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