PPC bootloader cache enabling

Mark A. Greer mgreer at mvista.com
Wed Dec 19 10:57:00 EST 2001


In the bootloader, we enable the L1 instruction cache and disable the L1
data cache.  If I understood the manuals correctly:

On a 750 (according to user's manual):
- The cache is unified so even though you have the L1 data cache
disabled, if you have L2 on, data will get cached there.

On a 7400/7410 (according to user's manuals):
- Last sentence in the first paragraph of section states, "if
the L1 data cache is disabled, the L2 cache must also be disabled."

In _setup_L2CR, the L2 cache is invalidated but its then enabled at the
end.  Am I missing something or is this a bug in _setup_L2CR?  If its a
bug, maybe we should rename it to invalidate_disable_l2 or something
like that?


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