high priority interrupts disabled - problem found

Dan Malek dan at embeddededge.com
Thu Dec 13 15:49:49 EST 2001

Steve Rossi wrote:

> So the problem is that mask & ack only masks the pending interrupts....

You are right.  Sorry, but I didn't have time today to reply to your first
message.  The problem with the 8xx (and 8260, and 4xx) is there isn't any
notion of priorities within the interrupt nesting.  As you have seen, any
interrupt can interrupt another, and although SIVEC (or the software bit
search) gives us the highest priority pending interrupt, once we enable
them again we get the next one delivered.

We should mask all lower priority interrupts, and the challenge is keeping
the proper nesting of the masks so the nested interrupts can be "unwound"
properly.  I'm thinking about it, and since you have been looking at the
functions so closely, if you have any implementation details let us know :-).
Perhaps we could look at the pending and enabled masks and unmask up to the
next pending interrupt to be serviced.


	-- Dan

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