Non-cacheable memory

Justin (Gus) Hurwitz ghurwitz at
Wed Aug 8 04:49:02 EST 2001

Several weeks ago I was attempting to allocate a region of non-cacheable
memory (required for my 603e based board's ethernet chip) and was told the
work was underway to get support for that into the kernel. I've not
checked up on that progress for a while now, so I thought I'd give it
another try:

Does the current 2_4_devel tree have support for allocating regions of
non-cachable memory? And, if so, what is the proper (or preferred) way of
doing this?

It sure would be nice if I could turn the board's L1 cache back on :)


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