User buffers and cache flushing.

[Greg Johnson]

Hi y'all,

The buffers I need to IDMA out to a peripheral are allocated by
the user with conventional malloc, and are rather dynamic so
the driver does not have a lot of control over them that I can
see.

So I have decided that I will be flushing the cache, either by
calling 'flush_page_to_ram' or 'flush_dcache_range'. Now, these
require a Kernel virtual address to work on (correct?), and the
caller has given me a User virtual address (through 'write (2)').
Therefore, before calling the flush function, I need to:

* Convert the User virtual address for each page to a Physical
  address by doing something along the lines of:

    pgd = pgd_offset(current->mm, addr)
    pmd = pmd_offset(pgd, addr)
    pte = pte_offset(pte, addr)
    etc.

* Convert the Physical address to a Kernel virtual address by
  calling 'phys_to_virt'.

Then I can call flush on each page I intend to IDMA out.

Does this sound reasonable?

Thanks

Greg.

Quoth Dan Malek:
>
>
> Greg Johnson wrote:
>
> > ....Since I
> > am not wanting to be double handling this data, and the data will
> > most likely be fragmented in memory,
>
> That's no problem, CPM buffer descriptors are made for that.
>
>
> > ....and call flush_dcache_range on each of these fragments.
>
> Depends upon how the data is handled.  In some cases I find it is
> faster to just map the pages uncached and skip the cache push.  Do
> some system design and analysis to determine what works best.
>
> > Have I overlooked anything? (other than the lack of support for IDMA
> > currently in the MPC8xx kernel)
>
> This is pretty trivial, considering all CPM devices use the same DMA
> engine as IDMA.  Take an existing driver, rip the guts of data comm
> out of it, and you nearly have the IDMA driver.
>
>
> 	-- Dan
>
>
>


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|               --== Greg Johnson ==--               |
| HW/SW Engineer      gjohnson at research.canon.com.au |
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