2.5 or 2.4 kernel profiling

[Brian Ford]

On Tue, 12 Dec 2000, Dan Malek wrote:

> Brian Ford wrote:
>
> > Are the explicit driver level calls to invalidate_dcache_range necessary
> > on the receive side,
>
> None of the cache management calls are necessary on the 8260 since the
> cache is snooped.  We are mixing processor types in this discussion,
> so be careful what you assume is necessary or works for a particular
> driver.  They are different.
>
Yes, I know.

Does your statement mean that 60x bus memory is mapped
_PAGE_COHERENT?  What is the exact meaning of the GBL bit in the FCRx
register?

I am confused about their relations.

--
Brian Ford
Software Engineer
Vital Visual Simulation Systems
FlightSafety International
Phone: 314-551-8460
Fax:   314-551-8444


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