[PATCH v7 0/4] PCI: Add support for resetting the Root Ports in a platform specific way

[Niklas Cassel]

On Wed, Mar 11, 2026 at 08:44:15PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Mar 11, 2026 at 08:09:53PM +0530, Manivannan Sadhasivam wrote:
> > On Wed, Mar 11, 2026 at 12:05:15PM +0100, Niklas Cassel wrote:
> > > On Tue, Mar 10, 2026 at 07:31:58PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > > > Changes in v7:
> > > > - Dropped Rockchip Root port reset patch due to reported issues. But the series
> > > >   works on other platforms as tested by others.
> > > 
> > > Are you referring to
> > > 
> > > ## On EP side:
> > > # echo 0 > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start && \
> > >   sleep 0.1 && echo 1 > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start
> > > 
> > > Then running pcitest only having 7 / 16 tests passed ?
> > > 
> > > If so, isn't that a problem also for qcom?
> > > 
> > 
> > No, tests are passing on my setup after link up.
> > 
> > > 
> > > There is no chance that the patch:
> > > "misc: pci_endpoint_test: Add AER error handlers"
> > > improves things in this regard?
> > > 
> > > Or will it simply avoid the "AER: device recovery failed" print?
> > > 
> > 
> > Yes, as mentioned in the commit message, it just avoids the AER recovery failure
> > message.
> > 
> 
> I also realized that Endpoint state is not saved in all the code paths. So the
> pci_endpoint_test driver has to save/restore the state also. But it is still not
> clear why that didn't help you.
> 
> Can you share the snapshot of the entire config space before and after reset
> using 'lspci -xxxx -s "0000:01:00"'?

If I don't add something like:

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 1eced7a419eb..9d7ee39164d4 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -1059,6 +1059,9 @@ static int pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
                return ret;
        }
 
+       pr_info("saving PCI state (irq_type: %d)\n", req_irq_type);
+       pci_save_state(pdev);
+
        return 0;
 }
 
@@ -1453,6 +1456,7 @@ static pci_ers_result_t pci_endpoint_test_error_detected(struct pci_dev *pdev,
 
 static pci_ers_result_t pci_endpoint_test_slot_reset(struct pci_dev *pdev)
 {
+       pci_restore_state(pdev);
        return PCI_ERS_RESULT_RECOVERED;
 }

On top of your patch.

Then all the BAR tests + MSI and MSI-X tests fail.

There is a huge difference in lspci -vvv output (as I guess is expected),
including all BARs being marked as disabled.


With the patch above. There is zero difference before/after reset, and all
the BAR tests pass. However, MSI/MSI-X tests still fail with:

# pci_endpoint_test.c:143:MSI_TEST:Expected 0 (0) == ret (-110) 
# pci_endpoint_test.c:143:MSI_TEST:Test failed for MSI1

ETIMEDOUT.

This suggests that pci_endpoint_test on the host side did not receive an
interrupt.

I don't know why, but considering that lspci output is now (with the
save+restore) identical, I assume that the problem is not related to
the host. Unless somehow the host will use a new/different MSI address
after the root port has been reset, and we restore the old MSI address,
but looking at the code, dw_pcie_msi_init() is called by
dw_pcie_setup_rc(), so I would expect the MSI address to be the same.


I will be very busy for a few weeks, so I don't have time to debug this.
If anyone wants to debug this on rk3588, I'm attaching the patches for
this new feature for rk3588 that can be applied on top of this series.

Personally, I'm fine with this series getting merged even though this
new feature will only be supported by the QCOM driver.
But, I don't understand how e.g. pci endpoint test can work on QCOM
platforms, after the root port has been reset, without something like
the save/restore diff above.


Kind regards,
Niklas