[PATCH 4/5] ASoC: fsl-asoc-card: exclude S20_3LE format due to clock limitations

[Shengjiu Wang]

The S20_3LE format (20-bit samples in 3 bytes) requires bit clock
frequencies that cannot be generated by i.MX SAI/ESAI hardware.

SAI/ESAI derive BCLK from MCLK using integer dividers only. S20_3LE
requires non-integer divider ratios with standard MCLK frequencies.
For example, 48kHz stereo needs 1.920 MHz BCLK, which requires a
divider of 6.4 from 12.288 MHz MCLK (not an integer).

Add a format constraint to exclude S20_3LE, preventing clock
configuration failures. Users should use S16_LE, S24_LE, or S32_LE
instead.

Signed-off-by: Shengjiu Wang <shengjiu.wang at nxp.com>
---
 sound/soc/fsl/fsl-asoc-card.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/sound/soc/fsl/fsl-asoc-card.c b/sound/soc/fsl/fsl-asoc-card.c
index 50d7a5f2d79e..36c789f15582 100644
--- a/sound/soc/fsl/fsl-asoc-card.c
+++ b/sound/soc/fsl/fsl-asoc-card.c
@@ -320,6 +320,16 @@ static int fsl_asoc_card_startup(struct snd_pcm_substream *substream)
 	static struct snd_pcm_hw_constraint_list constraint_channels;
 	int ret;
 
+	/*
+	 * Remove S20_3LE as the clock (sysclk, bclk) can't be acquired
+	 * due to non-integer divider ratios.
+	 */
+	ret = snd_pcm_hw_constraint_mask64(runtime,
+					   SNDRV_PCM_HW_PARAM_FORMAT,
+					   ~SNDRV_PCM_FMTBIT_S20_3LE);
+	if (ret)
+		return ret;
+
 	constraint_channels.list = priv->support_channels;
 	constraint_channels.count = priv->num_channels;
 	constraint_rates.list = priv->support_rates;
-- 
2.34.1