[PATCH] powerpc/perf: Update check for PERF_SAMPLE_DATA_SRC marked events

[Athira Rajeev]

> On 21 Apr 2026, at 8:36 PM, Shivani Nittor <shivani at linux.ibm.com> wrote:
> 
> The core-book3s PMU sampling code validates the SIER TYPE field
> when PERF_SAMPLE_DATA_SRC is requested. The SIER TYPE field
> indicates the instruction type and is only valid for
> random sampling (marked events). To handle cases observed where
> SIER TYPE could be zero even for marked events,validation was
> added to drop such samples and increment event->lost_samples.
> 
> However, this validation was applied to all samples,
> including continuous sampling. In continuous sampling mode,
> the PMU does not set the SIER TYPE field, so it remains zero.
> As a result, valid continuous samples were incorrectly
> treated as invalid and dropped. Fixed this by gating the
> SIER TYPE validation with mark_event, so the check runs only
> for marked (random) events. Continuous samples now skip this
> check and are recorded normally in the final data recording path.
> 
> Fixes: 2ffb26afa642 ("arch/powerpc/perf: Check the instruction type before creating sample with perf_mem_data_src")
> Signed-off-by: Shivani Nittor <shivani at linux.ibm.com>

The changes looks good to me.

Reviewed-by : Athira Rajeev <atrajeev at linux.ibm.com <mailto:atrajeev at linux.ibm.com>>

Thanks
Athira
> ---
> 
> arch/powerpc/perf/core-book3s.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
> index 8b0081441f85..2e6adf5b95c4 100644
> --- a/arch/powerpc/perf/core-book3s.c
> +++ b/arch/powerpc/perf/core-book3s.c
> @@ -2242,6 +2242,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
> const u64 last_period = event->hw.last_period;
> s64 prev, delta, left;
> int record = 0;
> + int mark_event = regs->dsisr & MMCRA_SAMPLE_ENABLE;
> 
> if (event->hw.state & PERF_HES_STOPPED) {
> write_pmc(event->hw.idx, 0);
> @@ -2304,9 +2305,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
> * In ISA v3.0 and before values "0" and "7" are considered reserved.
> * In ISA v3.1, value "7" has been used to indicate "larx/stcx".
> * Drop the sample if "type" has reserved values for this field with a
> - * ISA version check.
> + * ISA version check for marked events.
> */
> - if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
> + if (mark_event && event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
> ppmu->get_mem_data_src) {
> val = (regs->dar & SIER_TYPE_MASK) >> SIER_TYPE_SHIFT;
> if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31))) {
> -- 
> 2.47.3
>