RFI: powerpc cpus supporting BLRM for MSR_LE

[Gabriel Paubert]

Hi,


[sorry for the delay, I had forgotten this message in my drafts]

On Sat, Sep 13, 2025 at 02:45:54AM -0500, Segher Boessenkool wrote:
> Hi!
> 
> On Fri, Sep 12, 2025 at 08:21:10PM +0100, Mark Cave-Ayland wrote:
> > Whilst the patch is fairly complete, the problem I have is that there
> > doesn't appear to be a concise list of CPUs that use BLRM (as opposed to
> > proper LE memory accesses) when MSR_LE is enabled.
> 
> *All* older PowerPC have everything on the system busses in BE, and
> when the CPU has MSR[LE]=1 it just swaps some lanes somewhere where
> stuff is transfered to the execution cores.  Exactly how this is done
> is quite funky, but not-naturally-aligned accesses in LE mode always
> were disallowed anyway!
> 
> I'm not sure how LE is done on 970 (aka "G5"), a 64-bit core (it is
> derived from GQ, POWER4+).
> 

The 970 does not seem to have LE mode. I just had a look at the 970FX
documentation I have and both LE and ILE bits are marked as reserved.

Gabriel

> For the more current cores, since Power8 all LE and misaligned accesses
> are supported with hardly any delay at all (sometimes the hardware needs
> to do two memory accesses, but there is no exception and interrupt
> caused, etc.)  And the hardware does a real shift, a big fat barrel
> shifter in the load/store unit.
> 
> Oh, and also since P8 instructions in LE mode are stored byteswapped in
> memory, too (older CPUs had instructions in BE always).  This is done
> somewhere between the instruction cache and predecode.
> 
> > From what I can gather all 64-bit CPUs use proper LE memory accesses, but
> 
> They don't.
> 
> > it's not clear whether for 32-bit CPUs the use of BLRM can be derived from
> > the PVR or other CPU registers.
> 
> It is still not clear to me what "BLRM" really means.
> 
> > Can anyone provide any insight as to which CPUs make use of BLRM for MSR_LE?
> 
> *All* CPUs that use the 6xx bus simply swap *and duplicate* some byte
> lanes, in such a way that all naturally aligned accesses work as-if a
> "real LE access" was done.  You can investigate it on real hardware by
> seeing what happens to weird accesses.  There was something on the
> Dolphin (GCN and Wii emulator) mailing lists some years ago you might
> be able to find (I fail to currently, but I didn't look very far).
> 
> Btw:
> 
> >   g2               PVR 00810011
> 
> That is mpc82xx, which uses a "603e" core.  *All* 603 and 604 are called
> G2 (G1 was 601, G3 is 740/750, G4 is 7400/7450 (two quite different
> cores!), G5 is 970).
> 
> 
> Segher
>