(subset) [PATCH v6 0/7] Add support of IRQs to QUICC ENGINE GPIOs

[Christophe Leroy]

On Thu, 18 Sep 2025 18:23:20 +0200, Christophe Leroy wrote:
> The QUICC Engine provides interrupts for a few I/O ports. This is
> handled via a separate interrupt ID and managed via a triplet of
> dedicated registers hosted by the SoC.
> 
> Implement an interrupt driver for those IRQs then add change
> notification capability to the QUICC ENGINE GPIOs.
> 
> [...]

Applied, thanks!

[2/7] soc: fsl: qe: Change GPIO driver to a proper platform driver
      commit: 156460811def1ae699eebe40d9678e4ce3d1d9bc
[3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
      commit: e9713655b29a47d23cbf07aacf50b0ce8ee0a850

Best regards,
-- 
Christophe Leroy <christophe.leroy at csgroup.eu>