[PPC] Boot problems after the pci-v6.18-changes

[Manivannan Sadhasivam]

Hi Herve,

On Wed, Oct 15, 2025 at 01:58:11PM +0200, Herve Codina wrote:
> Hi Christian,
> 
> On Wed, 15 Oct 2025 13:30:44 +0200
> Christian Zigotzky <chzigotzky at xenosoft.de> wrote:
> 
> > Hello Herve,
> > 
> > > On 15 October 2025 at 10:39 am, Herve Codina <herve.codina at bootlin.com> wrote:
> > > 
> > > Hi All,
> > > 
> > > I also observed issues with the commit f3ac2ff14834 ("PCI/ASPM: Enable all
> > > ClockPM and ASPM states for devicetree platforms")  
> > 
> > Thanks for reporting.
> > 
> > > 
> > > Also tried the quirk proposed in this discussion (quirk_disable_aspm_all)
> > > an the quirk also fixes the timing issue.  
> > 
> > Where have you added quirk_disable_aspm_all?
> 
> --- 8< ---
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 214ed060ca1b..a3808ab6e92e 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2525,6 +2525,17 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
>   */
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
>  
> +static void quirk_disable_aspm_all(struct pci_dev *dev)
> +{
> +       pci_info(dev, "Disabling ASPM\n");
> +       pci_disable_link_state(dev, PCIE_LINK_STATE_ALL);

Could you please try disabling L1SS and L0s separately to see which one is
causing the issue? Like,

	pci_disable_link_state(dev, PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2);

	pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);

- Mani

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