[PPC] Boot problems after the pci-v6.18-changes

[Christian Zigotzky]

 > Bjorn Helgaas <helgaas at kernel.org> wrote:
 >
 > Oops, I made that fixup run too late.  Instead of the patch above, can
 > you test the one below?
 >
 > You'll likely see something like this, which is a little misleading
 > because even though we claim "default L1" for 01:00.0 (or whatever
 > your Radeon is), the fact that L0s and L1 are disabled at the other
 > end of the link (00:00.0) should prevent us from actually enabling it:
 >
 >  pci 0000:00:00.0: Disabling ASPM L0s/L1
 >  pci 0000:01:00.0: ASPM: default states L1
 >
 > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
 > index 214ed060ca1b..27777ded9a2c 100644
 > --- a/drivers/pci/quirks.c
 > +++ b/drivers/pci/quirks.c
 > @@ -2524,6 +2524,7 @@ static void quirk_disable_aspm_l0s_l1(struct 
pci_dev *dev)
 >  * disable both L0s and L1 for now to be safe.
 >  */
 > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, 
quirk_disable_aspm_l0s_l1);
 > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, 
quirk_disable_aspm_l0s_l1);
 >
 > /*
 >  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain

Hi Bjorn,

Thanks for your patch. I patched the RC3 of kernel 6.18 with your new 
patch and compile it again. Unfortunately the FSL Cyrus+ board doesn't 
boot with your new patch.

Sorry,

Christian

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