[PATCH v2] dt-bindings: interrupt-controller: Convert fsl,mpic-msi to YAML
Rob Herring
robh at kernel.org
Thu Jun 26 06:12:32 AEST 2025
On Wed, Jun 11, 2025 at 11:42:09AM +0200, J. Neuschäfer wrote:
> As part of a larger effort to bring various PowerPC-related bindings
> into the YAML world, this patch converts msi-pic.txt to YAML and moves
> it into the bindings/interrupt-controller/ directory. The conversion may
> necessarily be a bit hard to read because the binding is quite verbose.
>
> Signed-off-by: J. Neuschäfer <j.ne at posteo.net>
> ---
> Changes in v2:
> - Rebase on v6.16-rc1
> - Address Conor Dooley's review comments:
> - Add multiline marker (|) to preserve formatting
> - Split 'reg' list in second example
> - Rewrite version dependent information as an if/else schema
>
> Link to v1: https://lore.kernel.org/r/20250403-msipic-yaml-v1-1-f4248475714f@posteo.net
> ---
> ---
> .../interrupt-controller/fsl,mpic-msi.yaml | 161 +++++++++++++++++++++
> .../devicetree/bindings/powerpc/fsl/msi-pic.txt | 111 --------------
> 2 files changed, 161 insertions(+), 111 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..89db7742c28b3650207b361bfa6fbaf4e69ccc45
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mpic-msi.yaml
> @@ -0,0 +1,161 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale MSI interrupt controller
> +
> +description: |
> + The Freescale hypervisor and msi-address-64
> + -------------------------------------------
> +
> + Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
> + Freescale MSI driver calculates the address of MSIIR (in the MSI register
> + block) and sets that address as the MSI message address.
> +
> + In a virtualized environment, the hypervisor may need to create an IOMMU
> + mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
> + because of hardware limitations of the Peripheral Access Management Unit
> + (PAMU), which is currently the only IOMMU that the hypervisor supports.
> + The ATMU is programmed with the guest physical address, and the PAMU
> + intercepts transactions and reroutes them to the true physical address.
> +
> + In the PAMU, each PCI controller is given only one primary window. The
> + PAMU restricts DMA operations so that they can only occur within a window.
> + Because PCI devices must be able to DMA to memory, the primary window must
> + be used to cover all of the guest's memory space.
> +
> + PAMU primary windows can be divided into 256 subwindows, and each
> + subwindow can have its own address mapping ("guest physical" to "true
> + physical"). However, each subwindow has to have the same alignment, which
> + means they cannot be located at just any address. Because of these
> + restrictions, it is usually impossible to create a 4KB subwindow that
> + covers MSIIR where it's normally located.
> +
> + Therefore, the hypervisor has to create a subwindow inside the same
> + primary window used for memory, but mapped to the MSIR block (where MSIIR
> + lives). The first subwindow after the end of guest memory is used for
> + this. The address specified in the msi-address-64 property is the PCI
> + address of MSIIR. The hypervisor configures the PAMU to map that address to
> + the true physical address of MSIIR.
> +
> +maintainers:
> + - J. Neuschäfer <j.ne at posteo.net>
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - fsl,mpic-msi
> + - fsl,mpic-msi-v4.3
> + - fsl,ipic-msi
> + - fsl,vmpic-msi
> + - fsl,vmpic-msi-v4.3
> + - items:
> + - enum:
> + - fsl,mpc8572-msi
> + - fsl,mpc8610-msi
> + - fsl,mpc8641-msi
> + - const: fsl,mpic-msi
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Address and length of the shared message interrupt
> + register set
> + - description: Address of aliased MSIIR or MSIIR1 register for platforms
> + that have such an alias. If using MSIIR1, the second region must be
> + added because different MSI group has different MSIIR1 offset.
> +
> + interrupts:
> + minItems: 1
> + maxItems: 16
> + description:
> + Each one of the interrupts here is one entry per 32 MSIs, and routed to
> + the host interrupt controller. The interrupts should be set as edge
> + sensitive. If msi-available-ranges is present, only the interrupts that
> + correspond to available ranges shall be present.
> +
> + msi-available-ranges:
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + items:
> + items:
> + - description: First MSI interrupt in this range
> + - description: Number of MSI interrupts in this range
> + description:
> + Define which MSI interrupt can be used in the 256 MSI interrupts.
> + If not specified, all the MSI interrupts can be used.
> + Each available range must begin and end on a multiple of 32 (i.e. no
> + splitting an individual MSI register or the associated PIC interrupt).
> +
> + msi-address-64:
> + $ref: /schemas/types.yaml#/definitions/uint64
> + description:
> + 64-bit PCI address of the MSIIR register. The MSIIR register is used for
> + MSI messaging. The address of MSIIR in PCI address space is the MSI
> + message address.
> +
> + This property may be used in virtualized environments where the hypervisor
> + has created an alternate mapping for the MSIR block. See the top-level
> + description for an explanation.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +anyOf:
allOf
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,mpic-msi-v4.3
> + - fsl,vmpic-msi-v4.3
> + then:
> + properties:
> + interrupts:
> + maxItems: 16
Don't you mean 'minItems: 16'? Otherwise, this schema has no effect.
I can fix these up when applying.
> + description:
> + Version 4.3 implies that there are 16 shared interrupts, and they
> + are configured through MSIIR1.
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