[PATCH 2/5] powerpc/microwatt: Device-tree updates

[Paul Mackerras]

On Wed, Jan 29, 2025 at 04:36:14PM +1000, Nicholas Piggin wrote:
> On Wed Jan 29, 2025 at 8:52 AM AEST, Paul Mackerras wrote:
> > Microwatt now implements ISA v3.1 (SFFS compliancy subset), including
> > prefixed instructions, scv/rfscv, and the FSCR, HFSCR, TAR, and CTRL
> > registers.  The privileged mode of operation is now hypervisor mode
> > and there is no privileged non-hypervisor mode; the MSR[HV] bit is
> > forced to 1.
> 
> Cool. Lots of development in microwatt.
> 
> Come to think of it we should have put a broadcast-tlbie feature
> in there and you wouldn't need the other patch. That can go on
> the todo list I guess.

I thought about doing that, but it would add complexity and I'm not
sure it would actually have any measurable performance benefit.  When
I saw it was optional in the ISA for LCS and below, and that the
kernel has all the machinery for handling the cross-CPU invalidations
via IPI, it became very much the path of least resistance to use the
kernel machinery.

> system-call-vectored was available in ISA v3.0. Not that we do much
> with it at the moment IIRC, but there were dreams of wiring it in for
> compat guests. With that fixed,

Interesting.  I looked in my copy of v2.07 (PowerISA_V2.07_PUBLIC.pdf)
and it mentions rfscv in a couple of places, but has no description of
scv or rfscv.  I'll change it to v3.0.

Thanks,
Paul.