[PATCH 1/2] arch/powerpc/perf: Check the instruction type before creating sample with perf_mem_data_src

kernel test robot lkp at intel.com
Sat Jan 18 11:50:40 AEDT 2025


Hi Athira,

kernel test robot noticed the following build errors:

[auto build test ERROR on powerpc/next]
[also build test ERROR on powerpc/fixes linus/master v6.13-rc7 next-20250117]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Athira-Rajeev/arch-powerpc-perf-Update-get_mem_data_src-function-to-use-saved-values-of-sier-and-mmcra-regs/20250113-143059
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
patch link:    https://lore.kernel.org/r/20250113062818.33187-1-atrajeev%40linux.vnet.ibm.com
patch subject: [PATCH 1/2] arch/powerpc/perf: Check the instruction type before creating sample with perf_mem_data_src
config: powerpc-gamecube_defconfig (https://download.01.org/0day-ci/archive/20250118/202501180825.LpRG6wYe-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250118/202501180825.LpRG6wYe-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501180825.LpRG6wYe-lkp@intel.com/

All errors (new ones prefixed by >>):

>> arch/powerpc/perf/core-book3s.c:2303:22: error: use of undeclared identifier 'ISA207_SIER_TYPE_MASK'
                   val = (regs->dar & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
                                      ^
>> arch/powerpc/perf/core-book3s.c:2303:48: error: use of undeclared identifier 'ISA207_SIER_TYPE_SHIFT'
                   val = (regs->dar & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
                                                                ^
   2 errors generated.


vim +/ISA207_SIER_TYPE_MASK +2303 arch/powerpc/perf/core-book3s.c

  2222	
  2223	#define PERF_SAMPLE_ADDR_TYPE  (PERF_SAMPLE_ADDR |		\
  2224					PERF_SAMPLE_PHYS_ADDR |		\
  2225					PERF_SAMPLE_DATA_PAGE_SIZE)
  2226	/*
  2227	 * A counter has overflowed; update its count and record
  2228	 * things if requested.  Note that interrupts are hard-disabled
  2229	 * here so there is no possibility of being interrupted.
  2230	 */
  2231	static void record_and_restart(struct perf_event *event, unsigned long val,
  2232				       struct pt_regs *regs)
  2233	{
  2234		u64 period = event->hw.sample_period;
  2235		s64 prev, delta, left;
  2236		int record = 0;
  2237	
  2238		if (event->hw.state & PERF_HES_STOPPED) {
  2239			write_pmc(event->hw.idx, 0);
  2240			return;
  2241		}
  2242	
  2243		/* we don't have to worry about interrupts here */
  2244		prev = local64_read(&event->hw.prev_count);
  2245		delta = check_and_compute_delta(prev, val);
  2246		local64_add(delta, &event->count);
  2247	
  2248		/*
  2249		 * See if the total period for this event has expired,
  2250		 * and update for the next period.
  2251		 */
  2252		val = 0;
  2253		left = local64_read(&event->hw.period_left) - delta;
  2254		if (delta == 0)
  2255			left++;
  2256		if (period) {
  2257			if (left <= 0) {
  2258				left += period;
  2259				if (left <= 0)
  2260					left = period;
  2261	
  2262				/*
  2263				 * If address is not requested in the sample via
  2264				 * PERF_SAMPLE_IP, just record that sample irrespective
  2265				 * of SIAR valid check.
  2266				 */
  2267				if (event->attr.sample_type & PERF_SAMPLE_IP)
  2268					record = siar_valid(regs);
  2269				else
  2270					record = 1;
  2271	
  2272				event->hw.last_period = event->hw.sample_period;
  2273			}
  2274			if (left < 0x80000000LL)
  2275				val = 0x80000000LL - left;
  2276		}
  2277	
  2278		write_pmc(event->hw.idx, val);
  2279		local64_set(&event->hw.prev_count, val);
  2280		local64_set(&event->hw.period_left, left);
  2281		perf_event_update_userpage(event);
  2282	
  2283		/*
  2284		 * Due to hardware limitation, sometimes SIAR could sample a kernel
  2285		 * address even when freeze on supervisor state (kernel) is set in
  2286		 * MMCR2. Check attr.exclude_kernel and address to drop the sample in
  2287		 * these cases.
  2288		 */
  2289		if (event->attr.exclude_kernel &&
  2290		    (event->attr.sample_type & PERF_SAMPLE_IP) &&
  2291		    is_kernel_addr(mfspr(SPRN_SIAR)))
  2292			record = 0;
  2293	
  2294		/*
  2295		 * SIER[46-48] presents instruction type of the sampled instruction.
  2296		 * In ISA v3.0 and before values "0" and "7" are considered reserved.
  2297		 * In ISA v3.1, value "7" has been used to indicate "larx/stcx".
  2298		 * Drop the sample if "type" has reserved values for this field with a
  2299		 * ISA version check.
  2300		 */
  2301		if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
  2302				ppmu->get_mem_data_src) {
> 2303			val = (regs->dar & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
  2304			if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31))) {
  2305				record = 0;
  2306				atomic64_inc(&event->lost_samples);
  2307			}
  2308		}
  2309	
  2310		/*
  2311		 * Finally record data if requested.
  2312		 */
  2313		if (record) {
  2314			struct perf_sample_data data;
  2315	
  2316			perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
  2317	
  2318			if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE)
  2319				perf_get_data_addr(event, regs, &data.addr);
  2320	
  2321			if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
  2322				struct cpu_hw_events *cpuhw;
  2323				cpuhw = this_cpu_ptr(&cpu_hw_events);
  2324				power_pmu_bhrb_read(event, cpuhw);
  2325				perf_sample_save_brstack(&data, event, &cpuhw->bhrb_stack, NULL);
  2326			}
  2327	
  2328			if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
  2329							ppmu->get_mem_data_src) {
  2330				ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
  2331				data.sample_flags |= PERF_SAMPLE_DATA_SRC;
  2332			}
  2333	
  2334			if (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE &&
  2335							ppmu->get_mem_weight) {
  2336				ppmu->get_mem_weight(&data.weight.full, event->attr.sample_type);
  2337				data.sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
  2338			}
  2339			if (perf_event_overflow(event, &data, regs))
  2340				power_pmu_stop(event, 0);
  2341		} else if (period) {
  2342			/* Account for interrupt in case of invalid SIAR */
  2343			if (perf_event_account_interrupt(event))
  2344				power_pmu_stop(event, 0);
  2345		}
  2346	}
  2347	

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