[PATCH 3/4] PCI/ERR: Amend documentation with DPC and AER specifics

[Linas Vepstas]

On Fri, Aug 29, 2025 at 2:41 AM Lukas Wunner <lukas at wunner.de> wrote:
>
> +   On platforms supporting Downstream Port Containment, the link to the
> +   sub-hierarchy with the faulting device is re-enabled in STEP 3 (Link
> +   Reset). Hence devices in the sub-hierarchy are inaccessible until
> +   STEP 4 (Slot Reset).

I'm confused. In the good old days, w/EEH, a slot reset was literally turning
the power off and on again to the device, for that slot. So it's not so much
that the device becomes "accessible again", but that it is now fresh, clean
but also unconfigured. I have not studied DPC, but the way this is worded
here makes me think that something else is happening.

-- Linas