[PATCH] fsldma: Support 40 bit DMA addresses where capable

[Ben Collins]

On Tue, Apr 22, 2025 at 08:34:55AM -0500, Arnd Bergmann wrote:
> On Tue, Apr 22, 2025, at 04:49, Ben Collins wrote:
> > On 64-bit QorIQ platforms like T4240, the CPU supports 40-bit addressing
> > and memory configurations > 64GiB. The fsldma driver is limiting itself
> > to only 64GiB in all Elo configurations.
> >
> > Setup fsldma driver to make use of the full 40-bit addressing space,
> > specifically on the e5500 and e6500 CPUs.
>
...
> 
> - The driver just writes the DMA address as a 64-bit register,
>   so most likely the DMA device can in fact do wider addressing,
>   and any limitation is either in the bus or the available
>   memory
> 
> - SoCs that don't set a dma-ranges property in the parent bus
>   are normally still capped to 32 bit DMA. I don't see those
>   properties, so unless there is a special hack on those chips,
>   you get 32 bit DMA regardless of what DMA mask the driver
>   requests

I've yet to see a dma-ranges property in any of the Freescale PowerPC
device trees.

I'll check on this, but I think it's a seperate issue. The main thing is
just to configure the dma hw correctly.

> - If there are chips that have more than 64GB of RAM installed
>   but have a limitation in the way the DMA engine is wired
>   up to 36 bits, that should be reflected in the dma-ranges
>   property, not the device driver.
> 
> - If the limitation is indeed specific to the version of the
>   IP block, this would normally need to be detected based on
>   the compatible string of the DMA engine itself, not a compile
>   time setting.

So a little research shows that these 3 compatible strings in
the fsldma are:

fsl,elo3-dma:		40-bit
fsl,eloplus-dma:	36-bit
fsl,elo-dma:		32-bit

I'll rework it so addressing is based on the compatible string.

-- 
 Ben Collins
 https://libjwt.io
 https://github.com/benmcollins
 --
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