[PATCH v1 14/36] soc: fsl: cpm1: tsa: Add support for QUICC Engine (QE) implementation
kernel test robot
lkp at intel.com
Tue Jul 30 11:43:42 AEST 2024
Hi Herve,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.11-rc1 next-20240729]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Herve-Codina/soc-fsl-cpm1-qmc-Update-TRNSYNC-only-in-transparent-mode/20240730-001631
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20240729142107.104574-15-herve.codina%40bootlin.com
patch subject: [PATCH v1 14/36] soc: fsl: cpm1: tsa: Add support for QUICC Engine (QE) implementation
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20240730/202407300923.HVotne4K-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240730/202407300923.HVotne4K-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202407300923.HVotne4K-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/soc/fsl/qe/tsa.c:984:17: warning: cast to smaller integer type 'enum tsa_version' from 'const void *' [-Wvoid-pointer-to-enum-cast]
984 | tsa->version = (enum tsa_version)of_device_get_match_data(&pdev->dev);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +984 drivers/soc/fsl/qe/tsa.c
7f6697511df485 Herve Codina 2024-07-29 970
1d4ba0b81c1cf2 Herve Codina 2023-02-17 971 static int tsa_probe(struct platform_device *pdev)
1d4ba0b81c1cf2 Herve Codina 2023-02-17 972 {
1d4ba0b81c1cf2 Herve Codina 2023-02-17 973 struct device_node *np = pdev->dev.of_node;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 974 struct resource *res;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 975 struct tsa *tsa;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 976 unsigned int i;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 977 int ret;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 978
1d4ba0b81c1cf2 Herve Codina 2023-02-17 979 tsa = devm_kzalloc(&pdev->dev, sizeof(*tsa), GFP_KERNEL);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 980 if (!tsa)
1d4ba0b81c1cf2 Herve Codina 2023-02-17 981 return -ENOMEM;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 982
1d4ba0b81c1cf2 Herve Codina 2023-02-17 983 tsa->dev = &pdev->dev;
3d16c3ebcd1ae6 Herve Codina 2024-07-29 @984 tsa->version = (enum tsa_version)of_device_get_match_data(&pdev->dev);
3d16c3ebcd1ae6 Herve Codina 2024-07-29 985 switch (tsa->version) {
3d16c3ebcd1ae6 Herve Codina 2024-07-29 986 case TSA_CPM1:
3d16c3ebcd1ae6 Herve Codina 2024-07-29 987 dev_info(tsa->dev, "CPM1 version\n");
3d16c3ebcd1ae6 Herve Codina 2024-07-29 988 break;
b76939bef42d1d Herve Codina 2024-07-29 989 case TSA_QE:
b76939bef42d1d Herve Codina 2024-07-29 990 dev_info(tsa->dev, "QE version\n");
b76939bef42d1d Herve Codina 2024-07-29 991 break;
3d16c3ebcd1ae6 Herve Codina 2024-07-29 992 default:
3d16c3ebcd1ae6 Herve Codina 2024-07-29 993 dev_err(tsa->dev, "Unknown version (%d)\n", tsa->version);
3d16c3ebcd1ae6 Herve Codina 2024-07-29 994 return -EINVAL;
3d16c3ebcd1ae6 Herve Codina 2024-07-29 995 }
1d4ba0b81c1cf2 Herve Codina 2023-02-17 996
1d4ba0b81c1cf2 Herve Codina 2023-02-17 997 for (i = 0; i < ARRAY_SIZE(tsa->serials); i++)
1d4ba0b81c1cf2 Herve Codina 2023-02-17 998 tsa->serials[i].id = i;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 999
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1000 spin_lock_init(&tsa->lock);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1001
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1002 tsa->si_regs = devm_platform_ioremap_resource_byname(pdev, "si_regs");
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1003 if (IS_ERR(tsa->si_regs))
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1004 return PTR_ERR(tsa->si_regs);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1005
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1006 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "si_ram");
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1007 if (!res) {
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1008 dev_err(tsa->dev, "si_ram resource missing\n");
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1009 return -EINVAL;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1010 }
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1011 tsa->si_ram_sz = resource_size(res);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1012 tsa->si_ram = devm_ioremap_resource(&pdev->dev, res);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1013 if (IS_ERR(tsa->si_ram))
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1014 return PTR_ERR(tsa->si_ram);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1015
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1016 tsa_init_si_ram(tsa);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1017
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1018 ret = tsa_of_parse_tdms(tsa, np);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1019 if (ret)
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1020 return ret;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1021
7f6697511df485 Herve Codina 2024-07-29 1022 ret = tsa_setup(tsa);
7f6697511df485 Herve Codina 2024-07-29 1023 if (ret)
7f6697511df485 Herve Codina 2024-07-29 1024 return ret;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1025
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1026 platform_set_drvdata(pdev, tsa);
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1027
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1028 return 0;
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1029 }
1d4ba0b81c1cf2 Herve Codina 2023-02-17 1030
--
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