[PATCH v2 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support

[Russell Currey]

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote:
> ISA 3.1B introduces the Dynamic Execution Control Register (DEXCR).
> It
> is a per-cpu register that allows control over various CPU behaviours
> including branch hint usage, indirect branch speculation, and
> hashst/hashchk support.
> 
> Add some definitions and basic support for the DEXCR in the kernel.
> Right now it just
> 
>   * Zero initialises the DEXCR and HASHKEYR when a CPU onlines.
>   * Clears them in reset_sprs().
>   * Detects when the NPHIE aspect is supported (the others don't get
>     looked at in this series, so there's no need to waste a CPU_FTR
>     on them).
> 
> We initialise the HASHKEYR to ensure that all cores have the same
> key,
> so an HV enforced NPHIE + swapping cores doesn't randomly crash a
> process using hash instructions. The stores to HASHKEYR are
> unconditional because the ISA makes no mention of the SPR being
> missing
> if support for doing the hashes isn't present. So all that would
> happen
> is the HASHKEYR value gets ignored. This helps slightly if NPHIE
> detection fails; e.g., we currently only detect it on pseries.
> 
> Signed-off-by: Benjamin Gray <bgray at linux.ibm.com>
> 

LGTM.

Reviewed-by: Russell Currey <ruscur at russell.cc>