[PATCH] ASoC: fsl_sai: Enable BCI bit if SAI works on synchronous mode with BYP asserted

[Shengjiu Wang]

On Tue, May 30, 2023 at 6:30 PM Chancel Liu <chancel.liu at nxp.com> wrote:

> There's an issue on SAI synchronous mode that TX/RX side can't get BCLK
> from RX/TX it sync with if BYP bit is asserted. It's a workaround to
> fix it that enable SION of IOMUX pad control and assert BCI.
>
> For example if TX sync with RX which means both TX and RX are using clk
> form RX and BYP=1. TX can get BCLK only if the following two conditions
> are valid:
> 1. SION of RX BCLK IOMUX pad is set to 1
> 2. BCI of TX is set to 1
>
> Signed-off-by: Chancel Liu <chancel.liu at nxp.com>
>

Acked-by: Shengjiu Wang <shengjiu.wang at gmail.com>

Best regards
Wang Shengjiu

> ---
>  sound/soc/fsl/fsl_sai.c | 11 +++++++++--
>  sound/soc/fsl/fsl_sai.h |  1 +
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> index d9344025dc16..5e09f634c61b 100644
> --- a/sound/soc/fsl/fsl_sai.c
> +++ b/sound/soc/fsl/fsl_sai.c
> @@ -491,14 +491,21 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai,
> bool tx, u32 freq)
>         regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
>                            FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
>
> -       if (savediv == 1)
> +       if (savediv == 1) {
>                 regmap_update_bits(sai->regmap, reg,
>                                    FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
>                                    FSL_SAI_CR2_BYP);
> -       else
> +               if (fsl_sai_dir_is_synced(sai, adir))
> +                       regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx,
> ofs),
> +                                          FSL_SAI_CR2_BCI,
> FSL_SAI_CR2_BCI);
> +               else
> +                       regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx,
> ofs),
> +                                          FSL_SAI_CR2_BCI, 0);
> +       } else {
>                 regmap_update_bits(sai->regmap, reg,
>                                    FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
>                                    savediv / 2 - 1);
> +       }
>
>         if (sai->soc_data->max_register >= FSL_SAI_MCTL) {
>                 /* SAI is in master mode at this point, so enable MCLK */
> diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
> index 3eb994aef36a..8254c3547b87 100644
> --- a/sound/soc/fsl/fsl_sai.h
> +++ b/sound/soc/fsl/fsl_sai.h
> @@ -116,6 +116,7 @@
>
>  /* SAI Transmit and Receive Configuration 2 Register */
>  #define FSL_SAI_CR2_SYNC       BIT(30)
> +#define FSL_SAI_CR2_BCI                BIT(28)
>  #define FSL_SAI_CR2_MSEL_MASK  (0x3 << 26)
>  #define FSL_SAI_CR2_MSEL_BUS   0
>  #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
> --
> 2.25.1
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ozlabs.org/pipermail/linuxppc-dev/attachments/20230602/f4f1a18c/attachment.htm>