[PATCH v4 20/36] powerpc: Implement the new page table range API

[Christophe Leroy]

Le 10/07/2023 à 22:24, Matthew Wilcox a écrit :
> On Sat, Mar 18, 2023 at 09:19:04AM +0000, Christophe Leroy wrote:
>> void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
>> 		pte_t pte, unsigned int nr)
>> {
>> 	pgprot_t prot;
>> 	unsigned long pfn;
>> 	/*
>> 	 * Make sure hardware valid bit is not set. We don't do
>> 	 * tlb flush for this update.
>> 	 */
>> 	VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
>>
>> 	/* Note: mm->context.id might not yet have been assigned as
>> 	 * this context might not have been activated yet when this
>> 	 * is called.
>> 	 */
>> 	pte = set_pte_filter(pte);
>>
>> 	prot = pte_pgprot(pte);
>> 	pfn = pte_pfn(pte);
>> 	/* Perform the setting of the PTE */
>> 	for (;;) {
>> 		__set_pte_at(mm, addr, ptep, pfn_pte(pfn, prot), 0);
>> 		if (--nr == 0)
>> 			break;
>> 		ptep++;
>> 		pfn++;
>> 		addr += PAGE_SIZE;
>> 	}
>> }
> 
> I'd rather the per-arch code were as similar to each other and the
> generic implementation as possible.  Fewer bugs that way and easier
> for other people to make changes that have to touch every architecture
> in the future.

I understand your point but I dislike the idea of open coding pte 
manipulations when you have helpers for that. If you had used helpers 
from the begining you wouldn't have had the mishap you had in v4.