[PATCH 3/6] ASoC: fsl_micfil: Add support for PLL switch at runtime

[Shengjiu Wang]

On Thu, Jun 30, 2022 at 6:37 PM Mark Brown <broonie at kernel.org> wrote:

> On Thu, Jun 30, 2022 at 01:39:11PM +0800, Shengjiu Wang wrote:
>
> > +static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil,
> unsigned int sample_rate)
> > +{
> > +     struct device *dev = &micfil->pdev->dev;
> > +     u64 ratio = sample_rate;
> > +     struct clk *clk;
> > +     int ret;
> > +
> > +     /* Reparent clock if required condition is true */
> > +     if (!micfil->pll8k_clk || !micfil->pll11k_clk)
> > +             return 0;
> > +
> > +     ratio = do_div(ratio, 8000) ? CLK_11K_FREQ : CLK_8K_FREQ;
> > +
> > +     /* Get root clock */
> > +     clk = micfil->mclk;
> > +     if (IS_ERR_OR_NULL(clk)) {
> > +             dev_err(dev, "no mclk clock in devicetree\n");
> > +             return PTR_ERR(clk);
> > +     }
> > +
> > +     /* Disable clock first, for it was enabled by pm_runtime */
> > +     clk_disable_unprepare(clk);
> > +     fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
> > +                                  micfil->pll11k_clk, ratio);
> > +     ret = clk_prepare_enable(clk);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return 0;
> > +}
>
> Seems like more of this logic could be factored out into the reparent
> function if the target sample rate is passed in?
>

Yes, let me update.

Best regards
Wang Shengjiu
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