[RESEND PATCH] soc: fsl: qe: request pins non-exclusively

[Andy Shevchenko]

On Sun, Dec 04, 2022 at 03:55:19PM -0800, Dmitry Torokhov wrote:
> On Sun, Dec 04, 2022 at 01:10:19PM +0100, Arnd Bergmann wrote:
> > On Sun, Dec 4, 2022, at 05:50, Dmitry Torokhov wrote:
> > >
> > > SoC team, the problematic patch has been in next for a while and it
> > > would be great to get the fix in to make sure the driver is not broken
> > > in 6.2. Thanks!
> > 
> > I have no problem taking thsi patch, but I get a merge conflict that
> > I'm not sure how to resolve:
> > 
> > 
> > @@@ -186,23 -182,27 +180,43 @@@ struct qe_pin *qe_pin_request(struct de
> >         if (WARN_ON(!gc)) {
> >                 err = -ENODEV;
> >                 goto err0;
> > ++<<<<<<< HEAD
> >  +      }
> >  +      qe_pin->gpiod = gpiod;
> >  +      qe_pin->controller = gpiochip_get_data(gc);
> >  +      /*
> >  +       * FIXME: this gets the local offset on the gpio_chip so that the driver
> >  +       * can manipulate pin control settings through its custom API. The real
> >  +       * solution is to create a real pin control driver for this.
> >  +       */
> >  +      qe_pin->num = gpio_chip_hwgpio(gpiod);
> >  +
> >  +      if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
> >  +              pr_debug("%s: tried to get a non-qe pin\n", __func__);
> >  +              gpiod_put(gpiod);
> > ++=======
> > +       } else if (!fwnode_device_is_compatible(gc->fwnode,
> > +                                               "fsl,mpc8323-qe-pario-bank")) {
> > +               dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__);
> > ++>>>>>>> soc: fsl: qe: request pins non-exclusively
> >                 err = -EINVAL;
> > -               goto err0;
> > +       } else {
> > +               qe_pin->controller = gpiochip_get_data(gc);
> > +               /*
> > +                * FIXME: this gets the local offset on the gpio_chip so that
> > +                * the driver can manipulate pin control settings through its
> > +                * custom API. The real solution is to create a real pin control
> > +                * driver for this.
> > +                */
> > +               qe_pin->num = desc_to_gpio(gpiod) - gc->base;
> >         }
> > 
> > Could you rebase the patch on top of the soc/driver branch in the
> > soc tree and send the updated version?
> 
> I see, it conflicts with:
> 
> 	c9eb6e546a23 soc: fsl: qe: Switch to use fwnode instead of of_node
> 
> that is in next but not in soc/driver tree/branch.

That's due to no reaction on the patch [1] from Freescale maintainers (*).
Either soc subsystem can pull this [2] or your patch can go via
pin control subsystem.

*) Note, there is not Arnd's name nor soc mailing list in the MAINTAINERS
   regarding those files, so I had had no idea about the correct route of
   the change.

[1]: https://lore.kernel.org/lkml/20221005152947.71696-1-andriy.shevchenko@linux.intel.com/
[2]: https://lore.kernel.org/linux-gpio/Y3YY%2Fm0F%2FRh0jUc7@black.fi.intel.com/

-- 
With Best Regards,
Andy Shevchenko