[PATCH] powerpc/40x: Map 32Mbytes of memory at startup

[cp]

hi,
this is my first patch-test report.

Today I have successfully tested Christophe Leroy's patch.
I had to manually edit lines, but it worked with a kernel sized 9.1MByte :D

used toolchain:
- powerpc-unknown-linux-gnu-binutiles-v2.34
- powerpc-unknown-linux-gnu-gcc-v9.3.0

host:
- macmini-intel, Gentoo cross-compiler

target:
- AMCC PPC405GP

wrapper:
- cuboot

Applied to kernel-v5.2.1-vanilla

Attached I report here is the difference between the original file and mine.

Thanks guys!
Carlo

----------------
Map 32Mbytes rather than 16MB of memory at startup
--- arch/powerpc/kernel/head_40x.S.original     2021-09-27
16:32:04.536000000 -0000
+++ arch/powerpc/kernel/head_40x.S      2021-09-27 16:32:04.532000000 -0000
@@ -38,6 +38,8 @@
 #include <asm/export.h>
 #include <asm/asm-405.h>

+#include <linux/sizes.h> /* hack, include/linux/sizes.h defines "SZ_16M" */
+
 #include "head_32.h"

 /* As with the other PowerPC ports, it is expected that when code
@@ -839,18 +841,25 @@
        mtspr   SPRN_PID,r0
        sync

-       /* Configure and load one entry into TLB slots 63 */
+       /* Configure and load one entry into TLB slots 62/63 */ /* hacked */
        clrrwi  r4,r4,10                /* Mask off the real page number */
        ori     r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */

        clrrwi  r3,r3,10                /* Mask off the effective page number */
        ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))

-        li      r0,63                    /* TLB slot 63 */
-
+//-- hack begin
-----------------------------------------------------------------------------
+// TLB 63 is used for first 16M page
+// TLB 62 is for the second 16M page
+//        li      r0,63                    /* TLB slot 63 */ /* original */
+        li      r0,62                    /* TLB slot 62 */ /* hacked */
+// ------------------------------------------------------------------------------------------
        tlbwe   r4,r0,TLB_DATA          /* Load the data portion of the entry */
        tlbwe   r3,r0,TLB_TAG           /* Load the tag portion of the entry */
-
+// ------------------------------------------------------------------------------------------
+        addis   r4,r4,SZ_16M at h           /* added, hacked */
+        addis   r3,r3,SZ_16M at h           /* added, hacked */
+//-- hack end -----------------------------------------------------------------------------


        isync

        /* Establish the exception vector base