some problem about powepc 7448 board dcache enable

[山区里的孩子缺水喝]

Dear friend，

Good day.

This is jason from china.I am the os developer of powepc 7448 board.  Recently, I encountered a problem during development. I enabled L1 DCache during kernel startup. The code is as follows：	mfspr	8, 0x3f0	/* HID0 */ 
	ori	8, 8, (1<<14)|(1<<10)	/* HID0_DCE|HID0_DCFI*/ 	mtspr	0x3f0, 8	/* HID0 */ 	isync
 During the startup of my OS code, I first initialize the interrupt vector table, then set the page table to adopt the method of segment mapping (without bat mapping), and finally enable L1 Icache and L1 DCache(I don't enable L2 Cache).After Enable L1 DCache  The following happened：
1：The exception deliberately created by the software cannot enter normally, software instruction jump  or print  at the entry of the exception vector table get no effect, and the clock interrupt cannot be triggered normally.
2：Function calls and programs are executed normally, and the execution speed of test dead loop is increased by 20 ~ 60 times
3：The software instruction can jump to the exception vector table, and the contents of the exception vector table can be read normally
4：After DCache is enabled for a while  i disable it, the system works normally



I tried to do this：
1.Refresh the cache before and after starting the cache. L1 L2 cache is invalid and has no effect
2.The exception vector table uses a high address space and has no effect
3.Turn on the hid0 SPD bit, that is, turn off the cache prediction function, which has no effect
4.Configuring the first 16K separately, that is, adding cache and guard attributes to the MMU mapping attribute of the exception vector table, has no effect
5.Simply configure l2cr and enable L2 cache (no other L2 related registers are configured), which has no effect
6.Restoring hid0 to the reset value during system initialization has no effect
7.Replace the system load address to 0x30000 which has no effect

8.Try to use the dcache enable code  of uboot, VX and Linux to enable dcache, but there is no effect


My question is below:
1.whether L1 DCache can open before data mmu enable ?
2.is there something must to do before openning  L1 DCache 
3.the possible reason which lead to the exception  handle abnormally when openning HID0 dCache


I found out from the Linux community that you have some experience in this field before. I hope you can give me some advices.



Thanks & Best Regards,

jason
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ozlabs.org/pipermail/linuxppc-dev/attachments/20211107/2ff9e229/attachment.htm>