[PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument

[Andrew Morton]

On Sat, 15 May 2021 09:35:25 -0700 Guenter Roeck <linux at roeck-us.net> wrote:

> >  
> >  #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
> >  static inline void flush_pmd_tlb_range(struct vm_area_struct *vma,
>                  ^^^^
> >  				       unsigned long start, unsigned long end)
> > +{
> > +	return flush_pmd_tlb_pwc_range(vma, start, end, false);
>         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 
> Doesn't that cause build warnings/errors all over the place ?

It will, thanks.  I queued a fix.