[PATCH] powerpc/perf: Fix cycles/instructions as PM_CYC/PM_INST_CMPL in power10

[Athira Rajeev]

> On 08-Jul-2021, at 9:13 PM, Paul A. Clarke <pc at us.ibm.com> wrote:
> 
> On Thu, Jul 08, 2021 at 10:56:57PM +1000, Nicholas Piggin wrote:
>> Excerpts from Athira Rajeev's message of July 7, 2021 4:39 pm:
>>> From: Athira Rajeev <atrajeev at linux.vnet.ibm.cm>
>>> 
>>> Power10 performance monitoring unit (PMU) driver uses performance
>>> monitor counter 5 (PMC5) and performance monitor counter 6 (PMC6)
>>> for counting instructions and cycles. Event used for cycles is
>>> PM_RUN_CYC and instructions is PM_RUN_INST_CMPL. But counting of these
>>> events in wait state is controlled by the CC56RUN bit setting in
>>> Monitor Mode Control Register0 (MMCR0). If the CC56RUN bit is not
>>> set, PMC5/6 will not count when CTRL[RUN] is zero.
>> 
>> What's the acutal bug here, can you explain a bit more? I thought
>> PM_RUN_CYC is supposed to be gated by the runlatch.
> 
> Would this renaming break compatibility with existing tools that
> presume PM_RUN_CYC and PM_RUN_INST_CMPL exist generically?


Hi Paul,

Thanks for checking the patch.

No, this does not break compatibility with existing tools. Since the change is only for PMC5 and PMC6. Events PM_RUN_CYC and PM_RUN_INST_CMPL still behaves the same way since they are programmed in different PMC’s.

Thanks
Athira
> 
> PC