[PATCH v6 17/39] powerpc/fsl_booke/32: CacheLockingException remove args

Christophe Leroy christophe.leroy at csgroup.eu
Sat Jan 16 18:38:17 AEDT 2021



Le 16/01/2021 à 01:43, Nicholas Piggin a écrit :
> Excerpts from Christophe Leroy's message of January 16, 2021 3:14 am:
>>
>>
>> Le 15/01/2021 à 17:49, Nicholas Piggin a écrit :
>>> Like other interrupt handler conversions, switch to getting registers
>>> from the pt_regs argument.
>>>
>>> Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
>>> ---
>>>    arch/powerpc/kernel/head_fsl_booke.S | 6 +++---
>>>    arch/powerpc/kernel/traps.c          | 5 +++--
>>>    2 files changed, 6 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
>>> index fdd4d274c245..0d4d9a6fcca1 100644
>>> --- a/arch/powerpc/kernel/head_fsl_booke.S
>>> +++ b/arch/powerpc/kernel/head_fsl_booke.S
>>> @@ -364,12 +364,12 @@ interrupt_base:
>>>    	/* Data Storage Interrupt */
>>>    	START_EXCEPTION(DataStorage)
>>>    	NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
>>> -	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it, pass arg3 */
>>> +	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it3 */
>>>    	stw	r5,_ESR(r11)
>>> -	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it, pass arg2 */
>>> +	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it */
>>> +	stw	r4, _DEAR(r11)
>>>    	andis.	r10,r5,(ESR_ILK|ESR_DLK)@h
>>>    	bne	1f
>>> -	stw	r4, _DEAR(r11)
>>>    	EXC_XFER_LITE(0x0300, handle_page_fault)
>>>    1:
>>>    	addi	r3,r1,STACK_FRAME_OVERHEAD
>>
>> Why isn't the above done in patch 5 ?
> 
> I don't think it's required there, is it?

Ah yes, moving the 'stw' is needed only here.

But the comments changes belong to patch 5, you have done exactly similar changes there in 
kernel/head_40x.S

By the way, I think patch 17 could immediately follow patch 5 and patch 18 could follow patch 6.

> 
> Thanks,
> Nick
> 


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