[PATCH] selftests/powerpc: Fix L1D flushing tests for Power10

[Michael Ellerman]

Russell Currey <ruscur at russell.cc> writes:
> The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1
> perf event to count L1D misses.  The value of this event has changed
> over time:
>
> - Power7 uses 0x400f0
> - Power8 and Power9 use both 0x400f0 and 0x3e054
> - Power10 uses only 0x3e054
>
> Update these selftests to use the value 0x3e054 on P10 and later,
> fixing the tests from finding 0 events.

I wonder if we can just use the cache events that the kernel knows
about.

ie, switch the type to PERF_TYPE_HW_CACHE and the event to
PERF_COUNT_HW_CACHE_MISSES.

That would end up using the same event on power7 and power8:

$ git grep PERF_COUNT_HW_CACHE_MISSES arch/powerpc/perf/power{7,8,9,10}*.c
arch/powerpc/perf/power7-pmu.c: [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
arch/powerpc/perf/power8-pmu.c: [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
arch/powerpc/perf/power9-pmu.c: [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
arch/powerpc/perf/power10-pmu.c:        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
arch/powerpc/perf/power10-pmu.c:        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_DEMAND_MISS_L1_FIN,

On power9 and power10 it's using slightly different events. But I think
it should still work, because these tests just counts misses
with/without the various flushes enabled.

The distinction between loads that miss at execute vs finish shouldn't
matter, but you'd need to test.

The advantage would be we wouldn't then need to update the test again
for future CPUs.

cheers